ATI, Cadence and TSMC Produce Industry's First Fabless X Architecture Chip; Cadence X Architecture Design Solution Reduces Costs and Improves Performance of PCI-Express Graphics Processors

ANAHEIM, Calif.—(BUSINESS WIRE)—June 13, 2005— ATI Technologies Inc. (NASDAQ:ATYT) (TSX:ATY), Cadence Design Systems, Inc. (NYSE:CDN) (NASDAQ:CDN) and Taiwan Semiconductor Manufacturing Company (TSMC) (TSE:2330) (NYSE:TSM) have successfully produced the foundry industry's first X Architecture device.

The ATI chip is a high-performance, high-volume PCI-Express graphics processor designed for desktop and notebook computers. The X Architecture is a revolutionary new approach to chip design whereby diagonal interconnects are employed to reduce chip costs, increase performance and lower power consumption.

The ATI device was implemented using the Cadence(R) X Architecture design solution and manufactured using TSMC's 0.11-micron process. This implementation eliminated one metal layer from the original Manhattan design, reducing die costs. The new device is expected to enter volume production late in the year.

"The X Architecture opens up a host of new possibilities for innovation in chip design," said Greg Buchner, vice president of Engineering at ATI. "As the industry leader in advanced graphics and digital media processors, ATI has long been a pioneer in adopting new chip design technologies. Using the Cadence X Architecture design solution, we have been able to increase the performance envelope while reducing costs, providing new opportunities and possibilities within our PC and consumer businesses."

"Our multi-year collaboration with Cadence has yielded tangible results. We became the first foundry to develop X Architecture design rules. Today, we are in early engagement with customers on 90-nanometer X Architecture designs and are currently developing 65-nanometer X Architecture design rules," said Dr. Ping Yang, TSMC Vice President, R&D. "ATI's chip validates TSMC's production-readiness of the X Architecture as a viable design alternative."

The Cadence X Architecture design solution is the industry's first physical design solution that enables the pervasive use of diagonal routes and employs the familiar netlist-to-GDSII flow. While leveraging Cadence's industry-proven expertise in the Manhattan implementation, the solution draws on innovations in placement, routing, infrastructure and extraction technologies. Cadence X Architecture design solutions for TSMC's 0.13-micron and 0.11-micron process nodes are now available to select customers under Cadence's value-based business model.

"Cadence is committed to providing inventive solutions for our customers' market success," said Kalyan Thumaty, vice president and general manager of X Architecture, at Cadence. "We're excited to see that the technological innovations employed in the Cadence X Architecture design solution are enabling industry leaders such as ATI to meet challenging market requirements. The collaboration between ATI, Cadence and TSMC has produced compelling benefits and validated the production-readiness of our X Architecture design solution."

To bring the X Architecture into manufacturing reality, TSMC created extensive test structures to formulate competitive X Architecture design rules and developed a unique OPC model and mask making techniques. TSMC also created enhanced technology files to handle diagonal design rules and parasitic extraction.

In recognition of this successful design chain collaboration in delivering this design, ATI is joining the X Initiative, and becomes the first fabless chip design member company.

"We're elated to welcome ATI, the world's leading graphics chip maker, as the first fabless member of the X Initiative," said Aki Fujimura, X Initiative steering group member, the co-inventor of X Architecture and chief technology officer, New Business Incubation, at Cadence. "The fabrication of ATI's chip by TSMC caps our efforts to ready the global semiconductor supply chain for production of fabless chips using the X Architecture."

About ATI Technologies

ATI Technologies Inc. is the world leader in the design and manufacture of innovative 3D graphics and digital media silicon solutions. An industry pioneer since 1985, ATI is the world's foremost graphics processing unit (GPU) provider and is dedicated to delivering leading-edge performance solutions for the full range of PC and Mac desktop and notebook platforms, workstation, set-top and digital television, game console and handheld device markets. With 2004 revenues of approximately US $2 billion, ATI has more than 2,700 employees in the Americas, Europe and Asia. ATI common shares trade on NASDAQ (ATYT) and the Toronto Stock Exchange (ATY).

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 4,700 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

About TSMC

TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly-owned subsidiary, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. In early 2001, TSMC became the first IC manufacturer to announce a 90-nm technology alignment program with its customers. TSMC's corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.

About the X Architecture

The X Architecture, the first production-worthy approach to the pervasive use of diagonal interconnect, reduces the total interconnect, or wiring, on a chip by up to 20 percent and via-counts by up to 30 percent, resulting in significant improvements in chip area, performance, power and cost. For the past 20 years, chip design has been primarily based on the de facto industry standard "Manhattan" architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores by preserving the Manhattan geometry of metal layers one through three.

About the X Initiative

The X Initiative, a group of leading companies from throughout the semiconductor industry, is chartered with accelerating the availability and fabrication of the X Architecture, a revolutionary interconnect architecture based on the pervasive use of diagonal routing. The X Initiative's five-year mission is to provide an independent source of education about the X Architecture, to facilitate support and fabrication of the X Architecture through the semiconductor industry design chain, and to survey usage of the X Architecture to track its adoption. Representing leaders spanning the entire design-to-silicon supply chain, X Initiative members include: Applied Materials, Inc.; ARM; ASML Netherlands B.V.; ATI Technologies Inc., Cadence Design Systems, Inc.; Canon U.S.A. Inc.; Dai Nippon Printing (DNP); GDA Technologies, Inc.; HPL Technologies, Inc.; Hoya Corporation; IN2FAB Technology Ltd.; Infineon Technologies AG; JEOL, Ltd.; KLA-Tencor Corporation; Leica Microsystems AG; Matsushita Electric Industrial Co., Ltd.; MicroArk Co. Ltd.; Nikon Corporation; NuFlare Technology Inc.; PDF Solutions, Inc.; Photronics, Inc.; Prolific Inc.; RUBICAD Corporation; Sagantec; Sanyo Electric Co., Ltd.; Silicon Logic Engineering, Inc.; SiliconMap, LLC.; Silicon Valley Research Inc.; STMicroelectronics; Sycon Design, Inc.; Tensilica, Inc.; Toppan Photomasks, Inc.; Toppan Printing Co.; Toshiba Corporation; TSMC; UMC; Virage Logic, Inc.; Virtual Silicon Technology, Inc.; Zenasis Technologies, Inc.; and Zygo Corporation. Membership is open to all companies throughout the semiconductor design chain. Materials can be found at http://www.xinitiative.com.

Cautionary Note Regarding Forward-looking Statements

This release contains forward-looking statements (including, without limitation, information regarding semiconductor design, production and performance improvements resulting from the X Architecture, the compatibility of the X Architecture with current technology, the future success of X Architecture technology and the ability of certain of the X Initiative members to support the X Architecture) that involve risks and uncertainties that could cause the results of X Initiative members and other events to differ materially from managements' current expectations. Actual results and events may differ materially due to a number of factors including, among others: future strategic decisions made by the X Initiative members; failure of the X Architecture to enable the production of designs that are feasible and competitive with current designs or future alternatives; future strategic decisions made by X Initiative members or others that inhibit the development of the X Architecture; demand for advanced semiconductors that are developed using the X Architecture; cost feasibility of the production of semiconductors designed using the X Architecture; and the rapid pace of technological change in the semiconductor industry. The matters discussed in this press release also involve risks and uncertainties described in the most recent filings of the X Initiative members with the Securities and Exchange Commission. The X Initiative members, individually or collectively, assume no obligation to update the forward-looking information contained in this release.

Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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Bruce Chan, 408-894-2961
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Jon Carvill, 905-882-2600
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TSMC
Dan Holden, 408-382-7921
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Eureka Endo, 415-593-8404
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